1. Field of the Invention
This invention relates to a semiconductor integrated circuit including an insulated gate field effect transistor (hereinafter called xe2x80x9cIGFETxe2x80x9d), and a method of manufacturing the same, and more particularly to a semiconductor integrated circuit including an IGFET which is constituted by a gate electrode having regions composed of two or more IV group elements which are different from each other, and a method of manufacturing the same. More specifically, the invention relates to a semiconductor integrated circuit including an elevated or raised source drain electrode in a main electrode which is used as a source or drain electrode of an IGFET, and a method of manufacturing the same.
2. Description of the Related Art
As a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) for constituting a semiconductor integrated circuit is being minimized, a gate insulated film of the MOFET tends to be made much thinner. Further, in order to suppress short channel effect due to minimization, a complementary MOSFET tends to adopt a dual gate structure for an electrode. In the dual gate electrode structure, a gate electrode of an n-channel MOSFET is set to an n-type while a gate electrode of a p-channel MOSFET is set to a p-type.
The electrode having the dual gate structure is generally manufactured by a process for manufacturing ordinary complementary MOSFET (CMOS) without an increase in the number of manufacturing processes. Specifically, in an n-channel MOSFET, an n-type impurity is doped in order to make source and drain electrodes for an n-type semiconductor region. Simultaneously, the n-type impurity is doped into a gate electrode. With a p-channel MOSFET, a p-type impurity is doped so as to make source and drain electrodes for a p-type semiconductor region. Concurrent with this, the same p-type impurity is doped into a gate electrode. Ion implantation is performed for the doping process. The doped gate electrode is annealed in order that the doped impurity is diffused and activated. The gate electrode doped by the n-type impurity is set to the n-type while the gate electrode doped by the p-type impurity is set to the p-type.
As the MOSFET is being minimized, the source and drain electrodes thereof are required to be made shallow and to have low resistivity. An elevated electrode structure is most preferable in order to meet the foregoing requirements. In the elevated electrode structure, elevated electrodes are laid over a source electrode (a semiconductor region) and a drain electrode (a semiconductor region) on a surface of a substrate made of single crystal Si (silicon). Each elevated electrode is formed by an epitaxial growth layer grown on the single crystal Si substrate. The source and drain electrodes are formed by diffusing an impurity over the single crystal Si substrate using the elevated electrodes as solid diffusion sources.
In the foregoing structure, the source and drain electrodes are formed through diffusion from the surface of the single crystal Si substrate, so that a shallow junction can be obtained. Further, one elevated electrode is laid over the source electrode, and the other elevated electrode is laid over the drain electrode. Therefore, it is possible to reduce resistivity of the electrodes.
However, the following considerations have not been taken in the semiconductor integrated circuit including the foregoing MOSFET.
(1) Use of the dual gate electrode structure causes different problems in the n-channel MOSFET and p-channel MOSFET, respectively. In the p-channel MOSFET, when forming source electrode and drain electrode having shallow junctions, ion implantation is executed using BF2 (boron fluoride) ions which can accomplish shallow ion implantation distribution (profile) In such a case, F (fluoride) which is ion-implanted simultaneously with B (boron) infiltrates into a gate insulated film (gate oxide film), and promotes diffusion of B in the gate insulated film, so that B leaks through the substrate (channel forming region) from the gate electrode. Thinning of the gate insulated film due to the minimization enhances leakage of B. Even if there is no F, leakage of B occurs because of the thin insulated gate film. As a result, a threshold voltage of the p-channel MOSFET becomes variable, which unfortunately reduces electrical reliability of a semiconductor circuit.
Conversely, in the n-channel MOSFET, when forming source and drain electrodes having shallow junctions, As (arsenic) ions which diffuse slowly are used. In order to prevent an increase in the number of manufacturing processes, the source and drain electrodes are doped by As ions as an n-type impurity, similarly to the gate electrode. The As ions are suitable to form source and drain electrodes having shallow junctions (i.e. in order to make the source and drain electrodes shallow). However, a low diffusion speed of As makes it difficult for As to diffuse all over the gate electrode with a high concentration, which means that the gate insulated film of the gate electrode suffers from an insufficient As concentration. Especially, shallow source and drain electrodes tend to be annealed at a low temperature, which further promotes the insufficient As concentration on the gate insulated film of the gate electrode. Therefore, when gate bias is applied to the gate electrode during actual operation, a depletion layer is produced in the gate electrode, and a threshold voltage of the n-channel MOSFET is made variable. This inevitably lowers electrical reliability of the semiconductor integrated circuit.
(2) The lowered electrical reliability of the semiconductor integrated circuit is an obstacle for minimization of the MOSFET, and prevents further integration of the semiconductor integrated circuit.
(3) Japanese Patent Laid-Open Publication No. Hei 4-25176 discloses a technique to prevent leakage of B in a p-channel MOSFET. According to the publication, the gate electrode is composed of poly-crystal Si containing impurities such as Ge (germanium), and is doped by implanting B, which is effective in suppressing growth of grains of the poly-crystal Si in a heating process, and preventing B from diffusing along the grains. However, an existing gate electrode is usually provided with a silicide electrode which is formed thereon through silicidation, in order to accomplish low resistivity. The silicide electrode containing impurities such as Ge of the gate electrode suffers from a high resisisity. Therefore, it is very difficult to accelerate a switching operation of the MOSFET and reduce a power supply voltage.
(4) In the elevated electrode, B is used as the p-type impurity in order to form the source and drain electrodes of the p-channel MOSFET. B diffuses faster than As as the n-type impurity. Therefore, sufficient shallowing cannot be accomplished in the p-channel MOSFET, which prevents high integration of the semiconductor integrated circuit.
(5) Further, since B in the elevated electrode cannot have sufficiently high active concentration, the elevated electrode suffers from high resistivity. Therefore, it is very difficult to accelerate the switching operation of the p-channel MOSFET and reduce a power supply voltage.
(6) Research and development have in progress in order to form a silicide electrode in the elevated electrode and accomplish low resistivity in the elevated electrode. However, since it is impossible to minimize a contact resistance between the elevated electrode and the silicide electrode, it has been impossible to accelerate the switching operation of the MOSFET and reduce a power supply voltage.
This invention has been contemplated in order to overcome the foregoing problems of the related art. A first object of the invention is to provide a semiconductor integrated circuit including an insulated gate field effect transistor (IGFET) in which a gate electrode of the IGFET is protected against leakage of a doped impurity to a channel region in order to accomplish a reliable threshold voltage and improve electrical reliability.
It is a second object of the invention to maintain a sufficient concentration of the doped impurity all over the gate electrode and prevent formation of a depletion layer in the gate electrode, thereby accomplishing a reliable threshold voltage, and providing a semiconductor integrated circuit including the IGFET with improved electrical reliability.
A third object of the invention is to provide a semiconductor integrated circuit which accomplish the first and second objects simultaneously. Especially, the third object is intended to assure a reliable threshold voltage and to improve electrical reliability in a complementary IGFET having a p-channel type IGFET and an n-channel type IGFET.
A fourth object of the invention is to provide a semiconductor integrated circuit which includes a minimized IGFET and is highly integrated, while accomplishing any of the foregoing first to third objects.
According to a fifth object of the invention, a semiconductor integrated circuit is provided with an IGFET which has an accelerated switching speed and a reduced power supply voltage, and assures an accelerated circuit operation and a reduced power consumption, while accomplishing any of the first to third objects. Especially, it is possible to accelerate the switching operation of the IGFET and reduce the power supply voltage through reduction of a resistance of a silicide electrode formed on a gate electrode of the IGFET. Therefore, the semiconductor integrated circuit can accelerate its circuit operation and reduce a power consumption.
It is a sixth object of the invention to provide a method of manufacturing a semiconductor integrated circuit which can reduce the number of manufacturing steps, while accomplishing any of the first to fifth objects. Especially, the sixth object is intended to provide the method for manufacturing the semiconductor integrated circuit in which a complementary IGFET can be manufactured with a reduced number of steps.
A seventh object of the invention is to provide a semiconductor integrated circuit in which an IGFET includes an elevated electrode, and a shallow source electrode and a shallow drain electrode (i.e. main electrodes). Therefore, the semiconductor integrated circuit can be highly integrated through minimization of the IGFET.
It is an eighth object of the invention to provide a semiconductor integrated circuit which accomplishes the seventh object and in which an elevated electrode has low resistivity and a reduced power supply voltage. Therefore, the semiconductor integrated circuit can assure an accelerated circuit operation and a reduced power consumption.
A ninth object of the invention is to provide a semiconductor integrated circuit which accomplishes the seventh or eighth object and in which an elevated electrode and a silicide electrode have a low contact resistance. The semiconductor integrated circuit can assure an accelerated circuit operation and a reduced power consumption.
It is a tenth object of the invention to provide a method of manufacturing a semiconductor circuit which accomplishes the seventh to ninth objects and to reduce the number of manufacturing steps.
A final object of the invention is to provide a semiconductor integrated circuit which accomplish at least two or more of the first to tenth objects of the invention and a method of manufacturing such a semiconductor integrated circuit.
According to a first feature of the invention, there is provided a semiconductor integrated circuit including an IGFET of which gate electrode comprising: (a) a first region composed of at least a first IV group element and a second IV group element which are different from each other, and formed on a gate insulated film of a semiconductor substrate; and (b) a second region composed of the first IV group element and formed on the first region.
It is preferable that the first region of the gate electrode has a composition ratio of the second IV group element gradually or stepwise reduced in accordance with a distance from the gate insulated film.
The first IV group element for the gate electrode is Si (silicon), and the second IV group element is Ge (germanium) or C (carbon). The first region of the gate electrode preferable has a thickness which is larger than a width of a depletion layer produced in an Si electrode. A composition ratio of Ge in the first region is actually determined to be at least 0.1 or less. Either an Si layer which is 1 nm thick and is substantially free from the first IV group element Ge or a Ge layer which is 1 nm thick or less and is substantially free from Si may be present between the gate insulated film and the first region of the gate electrode.
The gate electrode of the p-channel IGFET preferably contains at least B. The gate electrode of the n-channel IGFET preferably contains at least As.
In the foregoing semiconductor integrated circuit, the gate insulated film of the gate electrode of the p-channel IGFET contains Ge or C which is the second IV group element, so that a diffusion speed of the B as the p-type impurity is reduced, and leakage of B into the channel region can be prevented. As a result, it is possible to stabilize a threshold voltage of the p-channel IGFET, and to improve electrical reliability of the semiconductor integrated circuit. Further, in the case of the n-channel IGFET, the gate insulated film of the gate electrode contains Ge or C in the second IV group element, which increases a diffusion speed of As as the n-type impurity, and maintains sufficient impurity distribution of As all over the gate electrode. Therefore, it is possible to prevent the gate electrode from being changed into a depletion layer, to stabilize a threshold voltage of the n-channel IGFET, and improve electrical reliability of the semiconductor integrated circuit. Especially, with the semiconductor integrated circuit including a complementary IGFET of the dual gate structure, use of the gate electrode composed of the first and second IV group elements can stabilize threshold voltages of both the p-channel and n-channel IGFETs at the same time. As a result, it is possible to minimize the IGFETs and promote integration of the semiconductor integrated circuit.
According to a second feature of the invention, the semiconductor integrated circuit having the first feature includes a silicide electrode which is formed in contact with the second region of the gate electrode of the IGFET and is substantially free from the second IV group element, i.g. Ge or C. The silicide electrode is actually constituted by a CoSiy or TiSiy film.
The silicide electrode substantially free from the second IV group element can have low resistivity, which is effective in accelerating the switching operation of the IGFET and reducing a power supply voltage. Therefore, the semiconductor integrated circuit can operate very quickly and reduce a power consumption.
In accordance with a third feature, a semiconductor integrated circuit comprises: an IGFET including a gate electrode which is provided with a first region composed of at least a first IV group element and a second IV group element which are different from each other, and formed on a gate insulated film on a semiconductor substrate, and a second region composed of a multiple element compound including at least the first and second IV group elements and metal, and formed on the first region; and (b) a silicide electrode formed in contact with the second region of the gate electrode, composed of the first IV group element and metal, and being substantially free from the second IV group element.
This semiconductor integrated circuit in which the second region of the gate electrode of the IGFET is composed of the multiple element compound is as effective as the semiconductor circuit having the second feature.
In accordance with a fourth feature, a method of manufacturing a semiconductor integrated circuit having an IGFET, wherein a gate electrode of the IGFET is manufactured by the steps of: (a) forming, on a gate insulated film on a semiconductor substrate, a first region composed of at least a first IV group element and a second IV group element which are different from each other, and forming, on the first region, a second region composed of the first IV group element; and (b) forming a silicide electrode through silicidation of at least a part of the second region of the gate electrode.
With the foregoing method, the silicide electrode is formed through silicidation of at least a part of the second region composed of the first IV group element, and is substantially free from the second IV group element (e.g. Ge or C). It is therefore possible to reduce resistivity of the silicide electrode without increasing the number of manufacturing steps. Alternatively, the silicide electrode may be made through silicidation of the second region completely, and be in direct contact with the first region of the gate electrode. In such a case, the silicide electrode is also substantially free from the second IV group element.
According to a fifth feature of the invention, a method of manufacturing a semiconductor integrated circuit including IGFETs comprises the steps of: (a) forming, on a gate insulated film, a first region composed of at least a first IV group element and a second IV group element which are different from each other, and forming, on the first region, a second region composed of the first IV group element, thereby obtaining a first gate electrode for an IGFET of a first conductive channel type and a second gate electrode for another IGFET of a second conductive channel type; (b) introducing a first conductive impurity into the first gate electrode and a second conductive impurity into the second gate electrode; and (c) forming a silicide electrode through silicidation of at least a part of the second region of the first gate electrode and at least a part of the fourth region of the second region. The step (b) is the same as a step of introducing a first conductive impurity into a source or drain electrode of the first conductive channel type IGFET. Further, the step (b) is the same as a step of introducing a second conductive impurity into the source or drain electrode of the second conductive channel type IGFET.
Further, in the complementary IGFET, the gate electrodes having the first and second regions are produced in the same manufacturing step, which is effective in reducing the number of manufacturing steps compared with when the gate electrodes are separately prepared in the complementary IGFET. Further, with the complementary IGFET, this method is effective in producing the semiconductor integrated circuit having the first and fourth features.
According to a sixth feature of the invention, a semiconductor integrated circuit comprises: (a) a semiconductor region of a first conductive type; (b) an epitaxial growth layer formed on a semiconductor region and including a first region composed of at least a first IV group element and a second IV group element that are different from each other, and a second region composed of the first IV group element; and (c) a silicide electrode formed on the second region of the epitaxial growth layer.
The semiconductor region is a source or drain electrode of the IGFET, and the epitaxial growth layer is an elevated source or drain electrode.
The first IV group element of the elevated source or drain electrode is Si, the second IV group element of the elevated source or drain electrode is Ge or C.
A composition ratio of Ge in the first region of the elevated source or drain electrode is preferably at least 0.1 or more, and a thickness of the first region is at least 2 nm from the semiconductor region.
The silicide electrode is made of a CoSiy or TiSiy layer which is substantially free from Ge.
In the case of a complementary IGFET, the elevated source or drain electrode on the main electrodes of the p-channel IGFET preferably contains at least B. The elevated electrode on the main electrodes of the n-channel IGFET preferably contains at least As.
In this semiconductor integrated circuit, the presence of the second IV group element in the epitaxial growth layer, i.e., the first region of the elevated electrode, is effective in reducing the diffusion speed of the impurity doped in the elevated electrode, particularly B as the p-type impurity. Since the junctions of the semiconductor region formed by diffusion of the impurity from the elevated electrode can be made shallow, both the source electrode and the drain electrode (main electrode) can be also made shallow, which is effective in improving integration of the semiconductor circuit. Further, the active concentration of the p-type impurity in the elevated electrode is large compared with in Si electrode, which raises carrier concentration (hole concentration) in the elevated electrode. Therefore, it is possible to reduce resisitivity of the and power source voltage of the elevated electrode, and to accelerate the circuit operation of the semiconductor circuit and power consumption thereof. Still further, the silicide electrode substantially free from the second IV group element has low resistivity, which is effective in accelerating the switching operation of the IGFET and reduce power consumption thereof. As a result, the semiconductor integrated circuit can accelerate its circuit operation and reduce its power consumption. If the elevated electrode in contact with the silicide electrode contains the second IV group element, an energy gap there between can be reduced, and a height of a Schottkey barrier can be also decreased. This is effective in lowering the contact resistance between the elevated electrode and the silicide electrode. The semiconductor integrated circuit can accelerate its circuit operation and reduce its power consumption.
In accordance with a seventh feature, a method of manufacturing a semiconductor integrated circuit comprises the steps of: (a) forming a semiconductor region on a main surface of a semiconductor substrate; (b) forming on the semiconductor region an epitaxial growth layer which includes a first region composed of a first IV group element and a second IV group element which are different from each other, and forming on the first region a second region composed of the first IV group element; and (c) forming a silicide electrode through silicidation of at least a part of the second region of the epitaxial growth layer.
In the foregoing method, the silicide electrode is substantially free from the second IV group element (e.g. Ge or C) since it is formed through silicidation of the second region composed of the first IV group element. Therefore, it is possible to reduce resistivity of the silicide electrode without increasing the number of manufacturing steps. Alternatively, the second region of the epitaxial growth layer may be subject to silicidation so that the silicide electrode may be in contact with the first region of the epitaxial growth layer. In such a case, the silicide electrode is also substantially free from the second IV group element.
According to an eighth feature of the invention, a semiconductor integrated circuit manufacturing method comprises the steps of: (a) forming a main electrode of an IGFET; (b) forming, on the main electrode, a first region composed of a first IV group element and a second IV group element which are different from each other, and forming, on the first region, a second region composed of the first IV group element, thereby forming an elevated electrode (epitaxial growth layer); and (c) forming a silicide electrode through silicidation of a part of the second region of the elevated electrode.
This method is as effective as the method according to the seventh feature.
In accordance with a ninth feature of the invention, a semiconductor integrated circuit comprises: (a) an IGFET including a gate electrode provided with a first region which is composed of at least a first IV group element and a second IV group element which are different from each other and formed on a gate insulated film of a semiconductor substrate, and a second region which is composed of the first IV group element and formed on the first region, and a main electrode, (b) an elevated electrode formed on the main electrode, and having a third region composed of a third IV group element and a fourth IV group element which are different from each other and a fourth region formed on the third region and composed of the third IV group element; (c) a first silicide electrode formed in contact with the second region of the gate electrode, and being substantially free from the second IV group element; and (d) a second silicide electrode formed in contact with the fourth region of the elevated electrode, and being substantially free from the fourth IV group element.
The semiconductor integrated circuit is as effective as the semiconductor integrated circuits having the first, second and sixth features.
In accordance with a tenth feature of the invention, a method of forming a semiconductor integrated circuit including an IGFET, comprising the steps of: (a) forming, on a gate insulated film on a semiconductor substrate, a first region composed of a first IV group element and a second IV group element which are different from each other, and forming, on the first region, a second region composed of the first IV group element, and forming a main electrode, thereby obtaining the IGFET, (b) forming, on the main electrode, a third region composed of a third IV group element and a fourth IV group element which are different from each other, and forming, on the third region, a fourth region composed of the third IV group element; (c) forming a first silicide electrode through silicidation of at least a part of the second region of the gate electrode, the silicide electrode being substantially free from the second IV group element; and (d) forming a second silicide electrode through silicidation of at least a part of the fourth region of the elevated electrode simultaneously with the step (c), the second silicide electrode being substantially free from the fourth IV group element.
The foregoing method can produce the semiconductor integrated circuit which is as effective as the semiconductor circuit having the fourth and seventh features.